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Miriam Leeser
PeerJ Editor
1,700 Points

Contributions by role

Editor 1,700

Contributions by subject area

Artificial Intelligence
Distributed and Parallel Computing
Graphics
Scientific Computing and Simulation
Software Engineering
Algorithms and Analysis of Algorithms
Mobile and Ubiquitous Computing
Spatial and Geographic Information Systems
Internet of Things
Computer Aided Design
Computer Architecture
Optimization Theory and Computation
Emerging Technologies
Neural Networks
Computer Education
Agents and Multi-Agent Systems
Computer Networks and Communications
Databases
World Wide Web and Web Science
Data Mining and Machine Learning
Security and Privacy
Data Science
Network Science and Online Social Networks

Miriam Leeser

PeerJ Editor

Summary

Miriam Leeser is Professor of Electrical and Computer Engineering at Northeastern University. She has been doing research in hardware accelerators, including FPGAs and GPUs, for decades, and has done ground breaking research in floating point implementations, unsupervised learning, medical imaging and privacy preserving data processing. She received her BS degree in Electrical Engineering from Cornell University, and Diploma and Ph.D. Degrees in Computer Science from Cambridge University in England. She has been a faculty member at Northeastern since 1996, where she is head of the Reconfigurable Computing Laboratory and a member of the Computer Engineering group. She is a senior member of ACM, IEEE and SWE. Throughout her career she has been funded by both government agencies and companies, including DARPA, NSF, Google, MathWorks and Microsoft. She is the recipient of an NSF Young Investigator Award and the prestigious Fulbright Scholar Award.

My research group website is: https://rcl.sites.northeastern.edu/

Computer Architecture Distributed & Parallel Computing Embedded Computing

Section Editor

Systems, Networks and Communication

Editorial Board Member

PeerJ Computer Science

Past or current institution affiliations

Northeastern University

Work details

Professor

Northeastern University
Electrical and Computer Engineering

PeerJ Contributions

  • Edited 9

Academic Editor on

August 5, 2025
Hardware implementation of FPGA-based spiking attention neural network accelerator
Shiyong Geng, Zhida Wang, Zhipeng Liu, Mengzhao Zhang, Xuelong Zhu, Yongping Dan
https://doi.org/10.7717/peerj-cs.3077
November 22, 2024
SH-SDS: a new static-dynamic strategy for substation host security detection
Yang Diao, Hui Chen, Wei Liu, Abdur Rasool
https://doi.org/10.7717/peerj-cs.2512
July 12, 2024
MonARCh: an actor based architecture for dynamic linked data monitoring
Burak Yönyül, Oylum Alatlı, Rıza Cenk Erdur
https://doi.org/10.7717/peerj-cs.2133
February 19, 2024
Teaching computer architecture by designing and simulating processors from their bits and bytes
Mustafa Doğan, Kasım Öztoprak, Mehmet Reşit Tolun
https://doi.org/10.7717/peerj-cs.1818
December 8, 2023
Modified graph-based algorithm to analyze security threats in IoT
Ferhat Arat, Sedat Akleylek
https://doi.org/10.7717/peerj-cs.1743
February 20, 2023
Bidirectional k-nearest neighbor spatial crowdsourcing allocation protocol based on edge computing
Jing Zhang, Qian Ding, Biao Li, Xiucai Ye
https://doi.org/10.7717/peerj-cs.1244
November 28, 2022
A survey of field programmable gate array (FPGA)-based graph convolutional neural network accelerators: challenges and opportunities
Shun Li, Yuxuan Tao, Enhao Tang, Ting Xie, Ruiqi Chen
https://doi.org/10.7717/peerj-cs.1166
March 2, 2020
A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study
Varsha Kakkara, Karthi Balasubramanian, B. Yamuna, Deepak Mishra, Karthikeyan Lingasubramanian, Senthil Murugan
https://doi.org/10.7717/peerj-cs.250
November 20, 2017
Solving the inverse heat conduction problem using NVLink capable Power architecture
Sándor Szénási
https://doi.org/10.7717/peerj-cs.138