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Woorham Bae received his B.S. and Ph.D. degrees in electrical and computer engineering from Seoul National University, Seoul, Korea, in 2010 and 2016, respectively.
In 2016, he was with the Inter-University Semiconductor Research Center, Seoul National University, Seoul, Korea. From 2017 to 2019, he was with the University of California, Berkeley, CA, as a Postdoctoral Researcher. He is currently a Senior Engineer with Ayar Labs, Santa Clara, CA. He is the author of Analysis and Design of CMOS Clocking Circuits for Low Phase Noise (London, UK: Institution of Engineering and Technology). His current research interests include integrated circuits for silicon photonics, high-speed I/O circuits and architectures, non-volatile memory systems, and agile hardware design methodology.
Dr. Bae serves as an Associate Editor of IEEE Access (2018~) and an Editorial Review Board of IEEE Solid-State Circuits Letters (2017~). He received the IEEE Circuits and Systems Society Outstanding Young Author Award in 2018, the Distinguished Ph.D. Dissertation Award from the Department of Electrical and Computer Engineering, Seoul National University in 2016, the IEEE Circuits and Systems Society Pre-Doctoral Scholarship in 2016, the IEEE Solid-State Circuits Society STG Award in 2015.