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Design and FPGA implementation of a Rössler-driven 4D-HCR-AES framework for image encryption

algorithms-and-analysis-of-algorithms
cryptography
optimization-theory-and-computation
security-and-privacy
internet-of-things

Abstract

Real-time secure transmission of digital images encounters substantial computational obstacles owing to the constraints of software-based encryption and the escalating throughput requirements in embedded systems. This paper introduces an innovative hardware-accelerated image encryption system that integrates the Advanced Encryption Standard (AES) in Cipher Feedback (CFB) and Galois Counter Mode (GCM) with a hyperchaotic Rössler system to improve security performance. The present paper reports on a highly efficient, hardware-implemented encryption system, the 4D-HCR-AES Framework, of real-time images that uses the four-dimensional hyperchaotic Rössler system to produce strong cryptographic keys that are strictly checked through the use of a hash algorithm, namely the SHA-512. The system is implemented on a PYNQ-Z2 FPGA board and uses parallel processing to bring about a 20% improvement in throughput (40.96 Mb/s) and a 12% improvement in operating frequency (160 MHz) over current chaos-enhanced methods, and this system only consumes 1.736 W of power. Security analysis helps to prove its stability with the level of entropy close to 8.0 and the correlation coefficients close to zero, as well as NPCR values mostly of 99.7%, which is why it is a perfect and resource-efficient solution to the need of secure image transmission in time-sensitive scenarios within the areas of healthcare, military surveillance, and IoT systems.
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